The present invention relates to accessing data in memory and, more particularly, to minimizing memory access time on a memory with multiplexed address inputs.
In data processing systems having multiplexed address input memory devices, such as dynamic random access memories (DRAMs), the amount of time required to access data (i.e., read data from memory or store data therein) in predetermined locations affects overall system performance. Due to the fact that many data addresses are used per second, a delay in accessing any one memory location or group of locations can be substantial over the course of significant lengths of time.
DRAMs are often logically structured into separate banks with rows and columns within the banks. Such an organization has been found to be a great aid to data accessing techniques, since intersections of elements can generally be accessed more rapidly using random access techniques than can individual memory elements using sequential or serial access techniques. Within this structure and organization, however, a great number of systems have been devised to minimize access time.
Since DRAMs are dynamic devices, precharging of voltage is required to reach or exceed predetermined thresholds to ensure proper operation of certain internal nodes. Data integrity is ensured only if precharging occurs.
The act of precharging, unfortunately, requires a significant amount of time--on the order of 50 nanoseconds on a 100 nanosecond DRAM. This means that about 50% of access time is used for precharging.
Conventionally, data accessing occurs on a purely random basis, so that precharging occurs for every data item, irrespective of where it is located and regardless of the location of the previously accessed data. Since precharging accounts for about half of access time, it is clear that by reducing the precharging requirement access time can be greatly minimized.
It has been found that for groups of data accesses in normal data processing applications, more than half of the time two data locations to be accessed immediately after one another are located in the same row, but in different columns, in DRAM. This statistic is especially relevant for executing programs in which instructions are stored in sequential locations. In those cases, over 75% of the time a data element (program instruction) is located in the same row of memory as the previously accessed data element. Of course, one cannot predict with certainty whether a location to be accessed will be near the previously accessed location. But since statistics are often in favor of such close proximity of data, it would be advantageous to exploit this phenomenon.
It would also be advantageous to avoid precharging when possible.
It would also be advantageous to provide a system for accessing data located close to previously accessed data on a more efficient basis.
It would also be advantageous to update the location of currently accessed data so that it can be compared to previously accessed data when necessary.